Memory Optimization of Dynamic Binary Translators for Embedded Platforms

Dynamic binary translators (DBTs) are becoming increasingly important because of their power and flexibility. DBT-based services are valuable for all types of platforms. However, the high memory demands of DBTs present an obstacle for embedded systems. Most research on DBT design has a performance focus, which often drives up the DBT memory demand. In this dissertation, we propose a memory-oriented approach to DBT design. We consider the class of translation-based DBTs and their sources of memory demand cached translated code, cached auxiliary code and DBT data structures. We explore aspects of DBT design that impact these memory demand sources and propose strategies to mitigate memory demand. We also explore optimizations for DBTs that handle memory demand by placing a limit on it, thereby replacing the memory demand problem with a performance degradation problem. Our optimizations that mitigate memory demand reduce the performance degradation. Additionally, we design approaches specific to these memory-limited DBTs. We mitigate memory demand by identifying path selection (trace selection and linking) as a DBT design aspect that influences both the relative and absolute sizes of the different sources of memory demand. We explore a comprehensive set of path selection strategies to propose one that addresses both memory efficiency and performance. For a given path selection, we identified auxiliary code as offering many opportunities for further optimizing the memory demand. We designed approaches to reduce the size of individual auxiliary code blocks and the count of auxiliary code blocks. These optimizations reduce memory demand as well as improve performance by reaching the memory limit less often. While reaching the memory limit less often reduces the time spent flushing, retranslation over-